IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 81

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

10-Gbps Ethernet PHY
Figure 3–30. 10GBASE-X PHY/Ethernet MAC Block Diagram
Note to
(1) This clock is the reference clock. It is called pll_inclk in the PHY (xaui_10g) module, but is called sysclk in the top-level design.
Table 3–56. Top-Level Transceiver Signals (Part 1 of 2)
© July 2010 Altera Corporation
cal_blk_clk
xaui_tx_data[3:0]
xaui_rx_data[3:0]
serdes_reset_n
serdes_sysclk
reconfig_clk
reconfig_togxb[<n>:0]
(Note 1)
Figure
Signal Name
3–30:
MAC/RS
When you select a PHY that includes a hard PCS and PMA, the PHY provides
sysclk to the MAC. A PLL in Tx PMA generates sysclk. The 64-bit SDR XGMII
interface between MAC and PHY is synchronous to this clock. The PCS drives a set of
signals, including rx_syncstatus, that reflect the status of the PCS and PMA. Their
status is recorded in the ALTGX status0 and ALTGX status1 registers.
Table 3–56
media. (For more information about the MAC PHY interface, refer to
Functional Description” on page
rs_tx_data
rs_tx_ctrl
serdes_sysclk
rs_rx_data
rs_rx_ctrl
rx_syncstatus
describes the signals of the XAUI interface that interface to the physical
Dir
O
O
I
I
I
I
I
Calibration clock. This clock runs the calibration block for the analog
blocks. The frequency of this clock should be between 10–125 MHz.
Tx XAUI link.
Rx XAUI link.
Reset for the PHY.
Clock synchronous with the MAC-PHY 64-bit SDR XGMII interface. This
clock also serves as the sysclk for the MAC.
Clock used for the reconfiguration block. The reconfig dynamically
configures the PMA to change signal characteristics. More details can be
found in appropriate device handbook. This input is optional for
Stratix II GX but is required for Stratix IV GX and Arria II GX. The frequency
range of this clock is 37.5–50 MHz for XAUI because it requires a Tx/Rx
dual-mode transceiver channel.
3-bit configuration input for the PMA. The width depends on the device and
also whether a soft or hard XAUI PCS has been selected.
Phase
Comp
FIFO
Tx PCS
PCS
Rx PCS
3–2.)
coreclock_out
PHY
Description
CDR & De-
Serializer
serializer
Tx PLL
Rx PLL
PMA
Bit
10-Gbps Ethernet IP Functional Description
XAUI Tx
XAUI Rx
pll_inclk
(1)
“MAC
3–55