IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 48
IP-10GETHERNET
Manufacturer Part Number
IP-10GETHERNET
Description
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer
Altera
Datasheet
1.IP-10GETHERNET.pdf
(86 pages)
Specifications of IP-10GETHERNET
Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Quartus II
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 48 of 86
- Download datasheet (3Mb)
3–22
Table 3–10. Client Rx FIFO Interface
10-Gbps Ethernet IP Functional Description
user_rx_dat[63:0]
user_rx_val
user_rx_sop
user_rx_eop
user_rx_mty[2:0]
user_rx_error
user_rx_vlan_tag
user_rx_vlan_vlan_tag
Signal Name
1
3.2.4.18.MAC FIFO Interface
Figure 3–20
Figure 3–20. RX MAC FIFO Interface
The Rx FIFO interface does not include a backpressure signal to stop the flow of data
from the Rx MAC. The sink must be able to consume data continuously from the
MAC.
Table 3–10
Client RX
Interface
Dir
describes the signals that comprise the client Rx FIFO interface.
O
O
O
O
O
O
I
I
illustrates the MAC FIFO Rx interface.
64-bit client or source data for transmission.
When asserted indicates that the rest of the signals in the interface are valid.
Asserted for one cycle to indicate the start of a packet.
Asserted for one cycle to indicate the end of a packet.
Specifies how many bytes of user_rx_dat[63:0] are empty when
user_rx_eop is asserted as follows:
Value
0
1
2
3
4
5
6
7
Indicates the current packet has an error. Asserted in conjunction with the
user_rx_eop signal.
Indicates that the received frame is a VLAN tagged frame.
Indicates that the received frame is a stacked VLAN tagged frame.
Rx FIFO
(Sink)
Valid Data Bits
user_rx_dat[63:0]
user_rx_dat[63:8]
user_rx_dat[63:16]
user_rx_dat[63:24]
user_rx_dat[63:32]
user_rx_dat[63:40]
user_rx_dat[63:48]
user_rx_dat[63:56]
user_rx_vlan_vlan_tag
user_rx_dat[63:0]
user_rx_val
user_rx_sop
user_rx_eop
user_rx_err
user_rx_mty[2:0]
user_rx_vlan_tag
Description
(Source)
Rx MAC
© July 2010 Altera Corporation
MAC Functional Description
PHY MAC RC
Interface
Related parts for IP-10GETHERNET
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: