IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 44

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–18
10-Gbps Ethernet IP Functional Description
Figure 3–16. Stacked VLAN Tagged Frame Format
3.2.4.10.Pause Frame Termination
Pause frames are terminated within the receive engine; they are not forwarded to the
receive FIFO unless the control register PAUSE_FWD bit is set to one in which case the
pause is processed and forwarded. The MAC determines if a pause frame is valid by
checking its CRC and frame length. The MAC extracts pause quanta (time to pause
the Tx traffic) in a valid pause frame and forwards them to the transmit engine.
Invalid pause frames are ignored. The flow control using pause frames is explained in
“Congestion and Flow Control Using Pause Frames” on page
3.2.4.11.Inter Packet Gap
IPG octets received are removed by the MAC Rx and are not forwarded to the client.
3.2.4.12.Pause Ignore
When this bit is set to one, the Pause frames are not processed, so that the MAC Tx
traffic is not affected by the valid pause frames.
3.2.4.13.Control Frame Enable
In normal operation, the Rx MAC terminates control frames other than pause frames.
If CNTL_FRM_ENA is set to one, the Rx MAC passes the control frame (but not pause
frames) to the Avalon-ST interface. Pause frames have their own control register.
The MAC processes pause frame control as control frames and not pause frames. The
Rx MAC terminates them in the same manner as other control frames unless the
CNTL_FRM_ENA bit specifies otherwise.
Frame Length
2 bytes
2 bytes
2
1 byte
6 bytes
1 bytes
6 bytes
6 bytes
2
2
0..1500/9000 bytes
0..38 bytes
4 bytes
bytes
bytes
bytes
Length/Type (VLAN Tag 0x8100)
Length/Type (VLAN Tag 0x8100)
Frame Check Sequence
Destination Address
Client Length/Type
Source Address
Payload Data
VLAN Info
VLAN Info
Preamble
SFD
Start
Pad
© July 2010 Altera Corporation
3–25.
Stacked VLANs
MAC Functional Description