IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 56

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–30
3.5. Software Programming Interface
Table 3–15. Avalon-MM Control and Status Register Interface
10-Gbps Ethernet IP Functional Description
avalon_clk
avalon_reset_n
avalon_address[8:0]
avalon_write
avalon_writedata[31:0]
avalon_waitrequest
avalon_read
avalon_readdata[31:0]
f
Signal
3.4.4.6.Local and Line Loopback used simultaneously
You can use both local and line loopbacks simultaneously. In this mode, the MAC Tx
data is sent to the MAC Rx data while the line Rx data is forwarded to the MAC Tx
data.
Host software can access the configuration and statistics registers over the
Avalon-MM interface. The Avalon-MM interface employes a standard
memory-mapped protocol that is typically used for control and status updates. The
following are key features of this interface:
■
■
■
For a more information about the Avalon-MM protocol refer to the
Specifications.
Table 3–15
Host software uses a parallel address bus, read, write, write data, and read data
signals to perform its write and read operations.
A client can insert wait states, if the read or write operation cannot to be
completed in the next clock cycle.
The 32-bit register interface is accessed using byte addresses.
lists the signals that comprise this interface.
Direction
O
O
I
I
I
I
I
I
Clock input.
Active low reset.
9 bit register word address. The word address is formed by
right-shifting the lower two bits of the byte address provided
by an 8-bit host. For example, a byte address of 0x5C
becomes a word address of 0x17.
Write request from the master.
Write data.
Output to request wait cycles.
Read request from the master,
Data read from the slave register.
Description
© July 2010 Altera Corporation
Software Programming Interface
Avalon Interface