IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 65

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Table 3–17. Command_Config Register Bit Descriptions (Part 2 of 3)
© July 2010 Altera Corporation
12:10 Reserved
21:16 Reserved
Bit(s)
13
14
15
22
23
24
25
26
7
8
9
PAUSE_FWD
PAUSE_IGNORE
TX_ADDR_INS
SW_RESET
Reserved
LOCAL_LOOP_ENA
NO_LGTH_CHECK
Reserved
FIFO_ERR_DISC
XOFF_GEN
CNTL_FRM_ENA
Bit Name
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
—
—
■
■
■
■
■
■
Reserved.
Reserved.
■
■
■
■
Reserved.
Receive pause frame forwarding. Terminates or forwards pause frames.
Ignore pause frame quanta.
Set address on transmit.
Software reset command. Setting this bit to 1 causes the IP core to disable
the transmit and receive logic, flush the receive FIFO, and reset the statistics
counters. This bit is automatically cleared when the software reset sequence
completes.
Local loopback enable. Setting this bit to 1 enables loopback. Frames sent
through the transmitter interface are looped back into the receiver interface at
the XGMII before the PCS.
The transition from normal operation to loopback and from loopback to
normal operation only occurs between frames. If the IP core is transmitting a
packet, the transition occurs after the EOP and when the frame is complete.
Idle characters are transmitted to the Ethernet when in local loopback.
Reserved.
Pause frame generation. If this bit is set to 1, the IP core generates a pause
frame with the pause quanta set to the value configured in the
pause_quant register, independent of the receive FIFO status.
Receive control frame enable bit.
Receive payload length check disable.
Enable discard in FIFO. In store forward mode only, discards error and
overflow frames if set to 1.
If this bit is set to 1, the IP core forwards pause frames to the user
application.
If this bit is set to 0, the IP core terminates and discards pause frames.
Setting this bit to 1 causes the IP core to ignore received pause frames.
Setting this bit to 0 causes the transmit process to stop for an amount of
time specified in the pause quanta within the pause frame.
If this bit is set to 1, the IP core overwrites the transmit frame source
address with the address configured in the mac_0 and mac_1 registers,
or in any of the supplemental address registers.
If this bit is set to 0, the IP core does not modify the source address.
If this bit is set to 1, the receive control frames with any opcode other than
0x0001 are accepted and forwarded to the Avalon-ST interface.
If this bit is set to 0, the receive control frames with any opcode other than
0x0001 are discarded.
If this bit is set to 0, the IP core checks the actual payload length of
received frames against the length/type field in the received frames.
No checking is done if this bit is set to 1.
Description
10-Gbps Ethernet IP Functional Description
3–39