IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 18

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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2.4. Functional Verification
Getting Started with the 10-Gbps Ethernet IP
10. Click Generate to generate the system. The 10-Gbps Ethernet variant is
Altera provides a simple test infrastructure for basic functional verification of the
customized IP core. This testbench is automatically generated when you generate
your 10-Gbps Ethernet IP core. The details of the verification environment and how to
use it is being described below.
The testbench consists of the following components:
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Figure 2–6
stored in clear text in <ip_lib>/eth_10g/tb.
Figure 2–6. Block Diagram of the Testbench
The testbench sends and checks received Ethernet frames. The maximum supported
frame size is 16 KBytes. It performs the following functions:
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eth_10ginst_0.v. A report file, <variation_name>.html describes the HDL files that
make up the design and the top-level signals.
An Avalon-ST client packet generator
Avalon-ST client packet checker
The 10-Gbps Ethernet device under test (DUT)
An XGMII Ethernet packet generator
An XGMII Ethernet packet checker
An Avalon-MM configuration module
Generates Ethernet frames and checks their validity
illustrates the top-level modules in the testbench. The testbench files are
Avalon-ST
Avalon-ST
Generator
Ethernet
Ethernet
Monitor
Slave 0
Slave 1
Frame
Frame
MDIO
MDIO
Simulation Parameters
Testbench
Reference
10-Gbps
Ethernet
Control
Design
Chapter 2: Getting Started with the 10-Gbps Ethernet IP
Generator
Ethernet
Ethernet
Monitor
XGMII
Frame
XGMII
Frame
© July 2010 Altera Corporation
Functional Verification