IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 45

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Table 3–7. Rx XGMII SDR interface
Table 3–8. Rx XGMII SDR interface
© July 2010 Altera Corporation
rs_rx_data[63:0]
rs_rx_ctrl[7:0]
xgmii_rx_clk
xgmii_rx_data[31:0]
xgmii_rx_ctrl[3:0]
Signal Name
Signal Name
3.2.4.14. MAC – PHY Rx Interface
Figure 3–17
Figure 3–17. SDR Rx XGMII Interface
Table 3–7
3.2.4.15. DDR Rx XGMII Interface
Table 3–8
3.2.4.16. Client Side Interfaces of the Rx Datapath
The Rx interfaces employ the Avalon-ST interface. You can include an optional FIFO
to buffer data between MAC and the client, or connect the MAC directly to the client.
Dir
Dir
Altera FPGA
O
O
I
I
I
describes the signals that comprise the standard DDR XGMII Rx interface.
describes the signals that comprise the SDR XGMII Rx interface.
illustrates the SDR XGMII interface for the Rx datapath.
8-lane data bus carrying bytes[7:0] from the PHY to the MAC.
8-bit signal from the PHY that indicates when a control octet is present on the
corresponding rs_rx_data lane
XGMII receive clock running at 156.25MHz. This clock should arrive
shifted 90
4-lane data bus carrying bytes[7:0] from the Rx MAC, changing value
on both edges of xgmii_rx_clk.
4-bit signal indicating when a control byte is present on corresponding
xgmii_rx_data lane.
MAC Rx
°
with respect to data and control.
rs_rx_data[63:0]
rs_rx_ctrl[7:0]
serdes_sysclk
Description
Description
Module
XGMII
(SDR)
10-Gbps Ethernet IP Functional Description
xgmii_rx_data[31:0]
xgmii_rx_ctrl[3:0]
xgmii_rx_clk
3–19