IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 49

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

ECC Options
Figure 3–21. FIFO MAC Rx Interface Timing Diagram
3.3. ECC Options
© July 2010 Altera Corporation
user_rx_vlan_vlan_tag
user_rx_data_valid
user_rx_data[63:0]
user_rx_vlan_tag
user_rx_mty[2:0]
avalon_st_clk
user_rx_error
user_rx_sop
user_rx_eop
f
1
Figure 3–21
3.2.4.19. Error Conditions on Rx Datapath
The Rx MAC indicates error conditions by asserting avl_st_rx_err. The following
error conditions are defined:
■
■
■
■
■
If your design includes a FIFO in store and forward mode, setting the
FIFO_ERR_DIS bit to 1 in the command_config register discards the errored
packets in the FIFO.
The 10-Gbps Ethernet IP core ECC feature implements single-bit error correction and
double-bit error detection (SECDED).
The ALTECC megafunction performs the ECC encoding and decoding for this IP
core. You can find additional information about this megafunction in the ALTECC
(Error Correction Code: Encoder/Decoder section of the
User
Received frame terminated early or with an error
Received frame has a CRC error
Received frame length does not match length field
Error characters received from PHY
Rx link fault, receive frame is too short (less than 64 bytes) or too long (longer than
the maximum specified length)
Guide.
illustrates the timing for this interface.
6
Integer Arithmetic Megafunctions
10-Gbps Ethernet IP Functional Description
5
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