IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 78

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–52
Table 3–52. MDIO Frame Formats (Read/Write)
Table 3–53. MDIO Frame Field Descriptions—Clause 22
Table 3–54. MDIO Frame Formats—Clause 45
10-Gbps Ethernet IP Functional Description
Read
Write
PRE
ST
OP
PHYAD
REDAD
TA
Data
Idle
Address
Write
Read
Name
Type
Preamble. 32 bits of logical 1 sent prior to every transaction.
Start indication. Standard MDIO (Clause 22): 0b01.
The opcode defines whether a read or write operation is performed:
■
■
The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set
to the value configured in the mdio_addr0 register.
Register address. Each PHY can have up to 32 registers.
Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for
read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2
bit of the turnaround phase.
16-bit data written to or read from the PHY device.
Between frames, the MDIO data signal is tristated.
1 ... 1
1 ... 1
PRE
0b10: a read operation is performed.
0b01: a write operation is performed.
Type
3.6.10.1.MDIO Frame Format (Clause 22)
The MDIO master controller communicates with the slave PHY device using frames.
A complete frame is 64-bits long and consists of 32-bit preamble, 14-bit command,
2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising edge of
the MDIO clock (MDC). The PHY management interface supports the standard MDIO
specification (IEEE803.2 Clause 22).
Table 3–53
3.6.10.2.MDIO Frame Format (Clause 45)
The MDIO master controller communicates with the slave PHY device using frames.
A complete frame is 64-bits long and consists of 32-bit preamble, 14-bit command,
2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising edge of
the MDIO clock (MDC). The PHY management interface supports the standard MDIO
specification (IEEE803.2 Clause 45).
ST
01
01
OP
10
01
describes the fields of the MDIO frame (Clause 22).
1 ... 1
1 ... 1
1 ... 1
PRE
PHYAD
AAAAA
AAAAA
ST
00
00
00
OP
00
01
11
RRRRR
RRRRR
REGAD
PRTAD
PPPPP
PPPPP
PPPPP
Description
Command
Table 3–52
Table 3–54
DEVAD
EEEEE
EEEEE
EEEEE
TA
Z0
10
Command
illustrates the MDIO formats.
describes the Clause 45 formats.
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
TA
10
10
Z0
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
AAAAAAAAAAAAAAAA
Data
Address/Data
© July 2010 Altera Corporation
Register Descriptions
Idle
Z
Z
Idle
Z
Z
Z
nd