IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 27

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3.1. Typical 10-Gbps Ethernet Systems
Figure 3–1. MAC Connecting to External Ethernet Device Over XAUI
© July 2010 Altera Corporation
Altera FPGA with 3.125 Gbps Transceivers
Interface
1
Client
This chapter provides a detailed description of Altera’s 10-Gbps Ethernet IP core. It
begins with a high-level overview of typical 10-Gbps Ethernet systems and then
provides detailed descriptions of the MAC, transmit (Tx) and receive (Rx) datapaths,
ECC, software programming model, register descriptions, PHY, clock domains, and
reset. It includes the following sections:
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Altera categorizes this IP core as a reference design, described on the Altera website
on the
This section provides top-level block diagrams of all of the variants that you can
create when you to customize your 10-Gbps Ethernet IP core.
Figure 3–1
device over XAUI.
Typical 10-Gbps Ethernet Systems
MAC Functional Description
ECC Options
Software Programming Interface
Register Descriptions
10-Gbps Ethernet PHY
Clocks and Reset
Module
Client
10-Gbps Ethernet Reference Design
illustrates a system with a MAC connecting an external 10-Gbps Ethernet
Avalon-ST
Interface
10-Gbps
Ethernet
MAC
10-Gbps
Ethernet
PHY
web page.
Interface
XAUI
3. 10-Gbps Ethernet IP
Functional Description
10-Gbps Ethernet IP Functional Description
or External
Optical or
Pluggable
Copper
Module
PHY