IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 76

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–50
Table 3–50. FIFO_TX_DROP_COUNT—Tx FIFO ECC Packets Dropped—Offset: 0x420
Table 3–51. FIFO_RX_DROP_COUNT—Rx FIFO ECC Packets Dropped—Offset: 0x424
3.6.9. ECC Testing
10-Gbps Ethernet IP Functional Description
[31:8]
[7:0]
[31:8]
[7:0]
Bits
Bits
Access
RC
Access
RC
Reserved
Number of ECC-detected packets dropped from Tx FIFO. This register saturates at
the value 255; after it reaches 255, it maintains this value until read. Reading this
register resets it automatically.
Reserved
Number of ECC-detected packets dropped from Rx FIFO. This register saturates at
the value 255; after it reaches 255, it maintains this value until read. Reading this
register resets it automatically.
This section describes how to test the ECC feature. This section assumes the following
definitions:
■
■
To test the ECC feature in your 10-Gbps Ethernet IP core, perform the following steps:
1. Reset the ECC management registers. All registers reset to the value 0.
2. Write values to the error mask registers to indicate the bit errors you wish to
3. Set the appropriate bits in the error insertion registers.
4. Run a test sequence that includes sending a packet.
5. Monitor the ecc_sbe, ecc_mbe, and ecc_packet_dropped signals to ensure
6. Repeat steps
When you enable the insertion of a bit error by performing steps
preceding instructions, the IP core implements error insertion differently for the Rx
and Tx FIFOs than for the Soft XAUI PCS FIFOs. In the case of the Rx and Tx FIFOs, if
you enable insertion during an idle cycle, the IP core inserts the error on the first cycle
of the next packet written to the FIFO. In the case of the Soft XAUI PCS FIFOs, because
data is written to the FIFOs continuously, the IP core inserts errors when requested. In
both cases, the error insertion bit clears within a few clock cycles after the error is
inserted.
Inserting a bit error in a Soft XAUI PCS FIFO affects two or three columns, which
could be in two different clock cycles.
Error mask registers—Includes all the ECC management registers except for the
ECC_FIFO_INS, ECC_XAUI_INS, and statistics registers.
Error insertion registers—Includes the ECC_FIFO_INS and ECC_XAUI_INS
registers.
insert.
the IP core detected the inserted errors correctly.
implementation.
2
to
4
until you are satisfied you have verified the ECC
Function
Function
© July 2010 Altera Corporation
2
and
0x0
0x0
0x0
0x0
Register Descriptions
HW Reset Value
HW Reset Value
3
in the