IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 29

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Figure 3–3. High-Level Block Diagram of the 10-Gbps Ethernet MAC
3.2.1. Transmit Datapath
© July 2010 Altera Corporation
Client Side
Management
Interface,
Datapath
Client Side
Interface,
Avalon-MM
Avalon-ST
Avalon-ST
Interface
Interface
Interface
32-bit
64-bit
64-bit
The Tx MAC module receives the client payload data with the destination and source
addresses and then adds, appends, or updates various header fields in accordance
with the configuration specified. The MAC does not modify the destination address
or the payload received from client. However, the Tx MAC module adds a preamble,
pads the payload to satisfy the minimum Ethernet frame payload of 64 bytes, and
calculates the CRC over the entire MAC frame. (If padding is added, it is also
included in CRC calculation.) The Tx MAC module can also modify the source
address, and insert interpacket gap (IPG) bytes when necessary.
(Optional)
(Optional)
Configuration and Status Registers
FIFO
FIFO
Tx
Rx
MAC Interface
64-bit FIFO
MDIO Interface to External PHY
Rx MAC
Tx MAC
64-bit Data Bus
Statistics Registers
SDR Interface
XGMI-like
10-Gbps Ethernet IP Functional Description
SDR-DDR
(optional)
Module
XGMII
MDIO
MDC
Standard
XGMII
3–3