IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 74

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–48
Table 3–38. ERR_XAUI_RATE_DATA_ECC_0—XAUI Rate FIFO Data Errors Word 0—Offset: 0x390
Table 3–39. ERR_XAUI_RATE_DATA_ECC_1—XAUI Rate FIFO Data Errors Word 1—Offset: 0x394
Table 3–40. ERR_XAUI_RATE_DATA_ECC_2—XAUI Rate FIFO Data Errors Word 2—Offset: 0x398
Table 3–41. ERR_XAUI_RATE_CTRL_ECC—XAUI Rate FIFO Control Errors—Offset: 0x39C
Table 3–42. ECC_COUNT_FIFO_TX_SBE—Recovered Tx FIFO ECC Errors—Offset: 0x400
Table 3–43. ECC_COUNT_FIFO_TX_MBE—Fatal Tx FIFO ECC Errors—Offset: 0x404
10-Gbps Ethernet IP Functional Description
[31:0]
[31:0]
[31:8]
[7:0]
[31:24] RW
[23:0]
[31:8]
[7:0]
[31:8]
[7:0]
Bits
Bits
Bits
Bits
Bits
Bits
Access
RW
Access
RW
Access
RW
RW
Access
RW
Access
RC
Access
RC
Errors inserted in bits [31:0] of the rate-matching FIFO data+ECC. For each bit
position, the value 1 indicates an error is inserted, and the value 0 indicates no error
is inserted.
Errors inserted in bits [63:32] of the rate-matching FIFO data+ECC. For each bit
position, the value 1 indicates an error is inserted, and the value 0 indicates no error
is inserted.
Reserved
Errors inserted in bits [71:64] of the rate-matching FIFO data+ECC. For each bit
position, the value 1 indicates an error is inserted, and the value 0 indicates no error
is inserted.
Reserved
Errors inserted in the 24-bit rate-matching FIFO control+ECC. For each bit position,
the value 1 indicates an error is inserted, and the value 0 indicates no error is
inserted.
Reserved
Number of single-bit errors detected and corrected in Tx FIFO. This register
saturates at the value 255; after it reaches 255, it maintains this value until read.
Reading this register resets it automatically.
Reserved
Number of multiple-bit errors detected in Tx FIFO. These errors are not corrected.
This register saturates at the value 255; after it reaches 255, it maintains this value
until read. Reading this register resets it automatically.
Function
Function
Function
Function
Function
Function
© July 2010 Altera Corporation
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Register Descriptions
HW Reset Value
HW Reset Value
HW Reset Value
HW Reset Value
HW Reset Value
HW Reset Value