IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 63

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Table 3–16. Control Interface Register Map (Part 6 of 7)
© July 2010 Altera Corporation
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
0x338
0x33C
0x340
Address
Offset
smac_2_1
smac_3_0
smac_3_1
MDIO clause 45
aFramesTransmittedOK_1 Packet and byte/octet counts for both
aFramesReceivedOK_1
aOctetsTransmittedOK_1
aOctetsReceivedOK_1
etherStatsOctets_1
etherStatsPkts_1
Reserved
ALTGX status0
Name
Supplemental address 2, bits 47:32.
Register bit 0 maps to bit 32 of the
address. Register bits 30:16 are
reserved. register bit 31 enables
address:
■
■
Supplemental address 3, bits 31:0.
Register bit 0 maps to bit 0 of the
address, bit 1 maps to bit 1 of the
address, and so on.
Supplemental address 3, bits 47:32.
Register bit 0 maps to bit 32 of the
address. Register bits 30:16 are
reserved. register bit 31 enables
address:
■
■
Reading or writing to this address
tells the MAC to perform an MDIO
read or write following the IEEE 802.3
specification. The address of the
register, device and port are specified
address 0x03C
transmitter and receiver are 64 bits
wide.
For more information about how to
access 64-bit registers, see
Statistics Counters” on page
See also
and
Reserved.
Status of the transceivers (XAUI
only).
■
■
■
■
For more information, refer to the
“Stratix IV Transceiver
chapter in the Stratix IV Device
Handbook.
0 to disable
1 to enable
0 to disable
1 to enable
0 pll_locked
1 rx_channelaligned
7:4 rx_freqlocked
11:8 rx_pll_locked
Table 3–20 on page
Table 3–18 on page 3–41
Description
Architecture”
3–42.
“64-Bit
3–43.
Access
10-Gbps Ethernet IP Functional Description
RW
RW
RW
RW
RO
RO
—
HW Reset
—
—
—
0
0
0
0
SW Reset
—
—
—
—
—
—
0
3–37