HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 95

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.4.3.1
5.4.4
Note:
5.5
Cortina Systems
In-Band Status
Carrier Sense (CRS) is generated by the PHY when a packet is received from the network
interface. CRS is indicated when:
Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only. Collision is
determined at the MAC by the assertion of TXEN being true while either CRS or RXDV are
true. The PHY will not assert CRS as a result of TXEN being true.
10/100 Mbps Functionality
The RGMII interface implements the 10/100 Mbps Ethernet Media Independent Interface
(MII) by reducing the clock rate to 25 MHz for 100 Mbps operation and 2.5 MHz for 10
Mbps. The TXC is generated by the MAC and the RXC is generated by the PHY. During
packet reception, the RXC is stretched on either the positive or negative pulse to
accommodate transition from the free-running clock to a data-synchronous clock domain.
When the speed of the PHY changes, a similar stretching of the positive or negative pulses
is allowed. No glitching of the clocks is allowed during speed transitions.
This interface operates at 10 Mbps and 100 Mbps speeds in the same manner as 1000
Mbps speed, although the data may be duplicated on the falling edge of the appropriate
clock. The MAC holds TX_CTL Low until it is operating at the same speed as the PHY.
The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode
MDIO Control and Interface
The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows the IXF1104 MAC to
monitor and control each of the PHY devices that are connected to the four ports of IXF1104
MAC when those ports are in copper mode.
The MDIO Master Interface block is implemented once in the IXF1104 MAC. The MDIO
Interface block contains the logic through which the user accesses the registers in PHY
devices connected to the MDIO/MDC interface, which is controlled by each port.
The MDIO Master Interface block supports the management frame format, specified by
IEEE 802.3, clause 22.2.4.5. This block also supports single MDI access through the CPU
interface and an autoscan mode. Autoscan allows the IXF1104 MAC MDIO master to read
all 32 registers of the per-port copper PHYs and store the contents in the IXF1104 MAC.
This provides external-CPU-ready access to the PHY register contents through a single
CPU read without the latency of waiting on the low-speed serial MDIO data bus for each
register access.
Scan of a single register with low-frequency operation takes approximately 25.6 µs. Scan of
a 32-register block takes approximately 820 µs, or 3.3 ms for all four ports. Autoscan data is
not valid until approximately 19.2 µs after enabling scan. These numbers scale by 7/50 for
high-frequency operation.
®
• RXDV = true.
• RXDV = false, RXERR = true, and a value of FF exists on the RXD[7:0] bits
• Carrier Extend, Carrier Extend Error, or False Carrier occurs (please reference the
IXF1104 4-Port Gigabit Ethernet Media Access Controller
simultaneously.
Hewlett-Packard* Version 1.2a RGMII Specification for details.).
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