HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 93

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.4.3
Table 26
Table 27
Cortina Systems
TX_ER and RX_ER Coding
To reduce interface power, the transmit error condition (TX_ER) and the receive error
condition (RX_ER) are encoded on the RGMII interface to minimize transitions during
normal network operation (refer to
provides signal definitions for RGMII.
RGMII Signal Definitions
The value of RGMII_TX_ER and RGMII_TX_EN are valid at the rising edge of the clock
while TX_ER is presented on the falling edge of the clock. RX_ER coding behaves in the
same way (see
TX_ER and RX_ER Coding Description
®
Condition
Receiving valid frame,
no errors
Receiving valid frame,
with errors
Receiving invalid frame
(or no frame)
Transmitting valid frame,
no errors
Transmitting valid frame
with errors
Transmitting invalid
frame (or no frame)
Note:
MAC Signal
RD[3:0]_n
TD[3:0]_n
IXF1104 4-Port Gigabit Ethernet Media Access Controller
IXF1104
RXC_0:3
TXC_0:3
RX_DV
TX_EN
Refer to
Standard
TD<3:0>
RD<3:0>
TX_CTL
RX_CTL
Figure 19
RGMII
Signal
Table
RXC
TXC
27,
RX_DV = true
Logic High on rising edge of RXC
RX_DV = true
Logic High on rising edge of RXC
RX_DV = false
Logic Low on rising edge of RXC
TX_EN = true
Logic High on rising edge of TXC
TX_EN = true
Logic High on rising edge of TXC
TX_EN = false
Logic Low on rising edge of TXC
for TX_CTL behavior, and
Source
MAC
MAC
MAC
PHY
PHY
PHY
Figure
Depending on speed, the transmit reference clock is 125 MHz, 25
MHz, or 2.5 MHz +/– 50ppm.
Contains register bits 3:0 on the rising edge of TXC and register bits
7:4 on the falling edge of TXC.
TXEN is on the leading edge of TXC.
TX_EN xor TX_ER is on the falling edge of TXC.
Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50
ppm.
Contains register bits 3:0 on the leading edge of RXC and register bits
7:4 on the trailing edge of RXC.
RX_DV is on the leading edge of RXC.
RX_DV or RXERR is the falling edge of RXC.
19, and
Table 27 on page 93
Figure
Figure 20
20).
Description
for RX_CTL behavior.
Description
RX_ER = false
Logic High on the falling edge of RXC
RX_ER = true
Logic Low on the falling edge of RXC
RX_ER = false
Logic Low on the falling edge of RXC
TX_ER =false
Logic High on the falling edge of TXC
TX_ER = true
Logic Low on the falling edge of TXC
TX_ER = false
Logic low on the falling edge of TXC
for the encoding method).
Table 26
Page 93