HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 39

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 3
Cortina Systems
SPI3 Interface Signal Descriptions (Sheet 2 of 8)
®
MPHY
TENB_0
TERR_0
TSOP_0
TEOP_0
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Signal Name
SPHY
TENB_0
TENB_1
TENB_2
TENB_3
TERR_0
TERR_1
TERR_2
TERR_3
TSOP_0
TSOP_1
TSOP_2
TSOP_3
TEOP_0
TEOP_1
TEOP_2
TEOP_3
Designator
Ball
C10
E11
B7
E2
C9
A8
K1
C7
E3
A7
E4
H5
J4
J8
J5
F3
Type
Input
Input
Input
Input
Standard
LVTTL
LVTTL
LVTTL
LVTTL
3.3 V
3.3 V
3.3 V
3.3 V
Description
Transmit Write Enable.
TENB_0:3 asserted causes an attached
PHY to process TDAT[n], TMOD, TSOP,
TEOP and TERR signals.
32-bit Multi-PHY mode: TENB_0 is the
enable bit for all 32 bits.
4 x 8 Single-PHY mode: TENB_0:3 bits
correspond to the respective TDAT[3:0]_n
channels and their associated control and
status signals.
Transmit Error.
TERR indicates that there is an error in the
current packet. TERR is valid when
simultaneously asserted with TEOP and
TENB.
32-bit Multi-PHY mode: TERR_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TERR_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit Start-of-Packet.
TSOP indicates the start of a packet and is
valid when asserted simultaneously with
TENB.
32-bit Multi-PHY mode: TSOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TSOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit End-of-Packet.
TEOP indicates the end of a packet and is
valid when asserted simultaneously with
TENB.
32-bit Multi-PHY mode: TEOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TEOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
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