HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 67

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 21
5.1.1.4
5.1.2
Cortina Systems
CRC Errored Packets Drop Enable Behavior
CRC Error Detection
Frames received by the MAC are checked for a correct CRC. When an incorrect CRC is
detected on a received frame, the RX FCSError RMON statistic counter increments for each
CRC errored frame. Received frames with CRC errors may optionally be dropped in the RX
FIFO (refer to
frames are sent to the SPI3 interface and may be dropped by the switch or system
controller.
Frames transmitted by the MAC are also checked for correct CRC. When an incorrect CRC
is detected on a transmitted frame, the TX CRCError RMON statistic counter increments for
each incorrect frame.
Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its
link partner take a temporary “Pause” in packet transmission. This allows the requesting
network node to prevent FIFO overruns and dropped packets, by managing incoming traffic
to fit its available memory. The temporary pause allows the device to process packets
already received or in transit, thus freeing up the FIFO space allocated to those packets.
The IXF1104 MAC MAC implements the IEEE 802.3x standard RX FIFO threshold-based
Flow Control in copper and fiber modes. When appropriately programmed, the MAC can
both generate and respond to IEEE standard pause frames in full-duplex operation. The
IXF1104 MAC also supports externally triggered flow control through the Transmit Pause
Control interface.
®
1. See
2. See
3. See
Note:
IXF1104 4-Port Gigabit Ethernet Media Access Controller
CRC Error
Pass
1
0
0
0
Table 90, RX Packet Filter Control ($ Port_Index + 0x19), on page
Table 122, RX FIFO Errored Frame Drop Enable ($0x59F), on page
Table 146, SPI3 Receive Configuration ($0x701), on page
x = “DON’T CARE”
1
Section 5.1.1.3.6, Filter CRC Error Packets, on page
ErroredFrame
Drop Enable
RX FIFO
0
0
1
x
2
Enable
RERR
x
1
0
x
3
When CRC Errored PASS = 1, CRC errored packets
are not filtered and are passed to the SPI3 interface.
They are not marked as bad, cannot be dropped, and
cannot be signaled with RERR.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are signaled with an RERR to the
switch or Network Processor.
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are not signaled with an RERR.
CRC errored packets are marked as bad, dropped in
the RX FIFO, and never appear at the SPI3 interface.
Note:
Packet sizes above the RX FIFO Transfer
Threshold (see
cannot be dropped in the RX FIFO and are
passed to the SPI3 interface. These packets
can optionally be signaled with RERR on the
SPI3 interface if the RERR Enable bit = 1.
205.
164.
188.
Actions
Table 127
66). Otherwise, the
through
Table
Page 67
130)