HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 91

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 25
Cortina Systems
GMII Interface Signal Definitions
®
IXF1104 MAC
IXF1104 4-Port Gigabit Ethernet Media Access Controller
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
RXC_0
RXC_1
RXC_2
RXC_3
CRS_0
CRS_1
CRS_2
CRS_3
TXC_0
TXC_1
TXC_2
TXC_3
COL_0
COL_1
COL_2
COL_3
Signal
GMII Standard
RXD<3:0>
GTX_CLK
TXD[7:0]
RX_CLK
TX_EN
TX_ER
RX_DV
RX_ER
Signal
CRS
COL
IXF1104
IXF1104
IXF1104
IXF1104
Source
MAC
MAC
MAC
MAC
PHY
PHY
PHY
PHY
PHY
PHY
Description
Transmit Reference Clock:
125 MHz for Gigabit operation.
MII operation for 10/100 Mbps operation is not
supported.
Transmit Data Bus:
Width of this synchronous output bus varies with the
speed/mode of operation. In 1000 Mbps mode, all 8
bits are used.
Transmit Enable:
Synchronous input that indicates Valid data is being
driven on the TXD[7:0] data bus.
Transmit Error:
Synchronous input to PHY causes the transmission of
error symbols in 1000 Mbps links.
Receive Clock:
Continuous reference clock is 125 MHz +/– 100 ppm.
Receive Data Bus:
Width of the bus varies with the speed and mode of
operation. In 1000 Mbps mode, all 8 bits are driven by
the PHY device.
Note: MII operation at 10/100 Mbps is not supported.
Receive Data Valid:
This signal is asserted when valid data is present on
the corresponding RXD bus.
Receive Error:
In 1000 Mbps mode, asserted when error symbols or
carrier extension symbols are received.
Always synchronous to RX_CLK.
Carrier Sense:
Asserted when valid activity is detected at the line-
side interface.
Collision:
Asserted when a collision is detected and remains
asserted for the duration of the collision event. In full-
duplex mode, the PHY should force this signal Low.
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