HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 106

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Note:
5.7.3.1
5.7.3.2
Note:
Cortina Systems
The specific interface in the IXF1104 MAC supports only a subset of the full I²C interface,
and only the features required to support the Optical Module Interfaces are implemented.
This leads to the following support features.
The I
coherency when reading two-byte registers.
I
In the IXF1104 MAC, the entire I²C interface is controlled through the following two
registers:
These registers can be programmed by system software using the CPU interface.
I
To perform a read operation using the I
Figure 24
The user software ensures the order of the contiguous accesses required to read the High
and Low bytes of 16-bit-wide PHY registers.
®
1. Initialize the Control register by setting the following values:
2. Set the Device ID field to 0xA and the register address (bits 10:8) to 0x0 to access the
3. Set the Device ID field to 0xA and the Register Address [10:8] between the values of
4. Poll the Read_Valid field, bit 20. The read data is available when this bit is set to 0x1.
2
2
• Single I
• Four per-port I
• The interface has both read and write functionality.
• Due to the single internal optical module controller, only one optical module may be
• The I
•
•
IXF1104 4-Port Gigabit Ethernet Media Access Controller
C Control and Data Registers
C Read Operation
unnecessary signals use.
module requirement that all modules must be addressed as 00h.
accessed at any one time. Each access contains a single register Read. Since these
register accesses will most likely be done during power-up or discovery of a new
module, these restrictions should not affect normal operation.
Table 154, I
Table 155, I
a. Enable the I
b. Initiate the I
c. Select the port by using bits [17:16].
d. Select the Read mode of operation by setting bit [15] to 0x1.
e. Select the Device ID by setting bits [14:11].
f.
fiber module serial E2PROM. Setting the Device ID field to 0xA and the Register
Address [10:8] to 0x0 permits read-only access.
0x1 and 0x7 to access the PHY registers.
2
C interface only supports random single-byte reads and does not guarantee
Select the register address by setting bits [10:0].
2
C interface supports byte write accesses to the full address range.
shows an 8-bit read access.
2
C_CLK pin connected to all optical modules and implemented to save
2
2
C Control Ports 0 - 3 ($0x79B), on page 212
C Data Ports 0 - 3 ($0x79F), on page 212
2
C_DATA signals (I²C Data[3:0]) are required because of the optical
2
2
C transfer by setting bit [24] of the control register to 0x1.
C Controller by setting bit [25] to 0x1.
2
C interface, use the following sequence:
Page 106