HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 19

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
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Cortina Systems
Auto-Negotiation Next Page Transmit ($ Port Index + 0x67) ...................................................... 179
Port Enable ($0x500)................................................................................................................... 180
Interface Mode ($0x501) ............................................................................................................. 180
Link LED Enable ($0x502)........................................................................................................... 181
MAC Soft Reset ($0x505)............................................................................................................ 181
MDIO Soft Reset ($0x506) .......................................................................................................... 182
CPU Interface ($0x508)............................................................................................................... 182
LED Control ($0x509).................................................................................................................. 182
LED Flash Rate ($0x50A)............................................................................................................ 183
LED Fault Disable ($0x50B) ........................................................................................................ 183
JTAG ID ($0x50C) ....................................................................................................................... 184
RX FIFO High Watermark Port 0 ($0x580).................................................................................. 184
RX FIFO High Watermark Port 1 ($0x581).................................................................................. 185
RX FIFO High Watermark Port 2 ($0x582).................................................................................. 185
RX FIFO High Watermark Port 3 ($0x583).................................................................................. 185
RX FIFO Low Watermark Port 0 ($0x58A) .................................................................................. 186
RX FIFO Low Watermark Port 1 ($0x58B) .................................................................................. 186
RX FIFO Low Watermark Port 2 ($0x58C).................................................................................. 186
RX FIFO Low Watermark Port 3 ($0x58D).................................................................................. 187
RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)....................................... 187
RX FIFO Port Reset ($0x59E)..................................................................................................... 187
RX FIFO Errored Frame Drop Enable ($0x59F).......................................................................... 188
RX FIFO Overflow Event ($0x5A0) ............................................................................................. 189
RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)......................................... 189
RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2) .......................................................... 190
RX FIFO Padding and CRC Strip Enable ($0x5B3) .................................................................... 191
RX FIFO Transfer Threshold Port 0 ($0x5B8)............................................................................. 191
RX FIFO Transfer Threshold Port 1 ($0x5B9)............................................................................. 192
RX FIFO Transfer Threshold Port 2 ($0x5BA) ............................................................................ 192
RX FIFO Transfer Threshold Port 3 ($0x5BB) ............................................................................ 193
TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) ............................................................. 193
TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................... 195
TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617)................................................ 196
TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E)................................................. 197
TX FIFO Port Reset ($0x620)...................................................................................................... 198
TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624) ....................................... 199
TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629) ......................................... 200
TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630).................................................. 200
TX FIFO Port Drop Enable ($0x63D) .......................................................................................... 201
MDIO Single Command ($0x680) ............................................................................................... 201
MDIO Single Read and Write Data ($0x681) .............................................................................. 202
Autoscan PHY Address Enable ($0x682).................................................................................... 202
MDIO Control ($0x683) ............................................................................................................... 202
SPI3 Transmit and Global Configuration ($0x700)...................................................................... 203
SPI3 Receive Configuration ($0x701) ......................................................................................... 205
Address Parity Error Packet Drop Counter ($0x70A) .................................................................. 208
TX Driver Power Level Ports 0 - 3 ($0x784)................................................................................ 208
TX and RX Power-Down ($0x787) .............................................................................................. 209
RX Signal Detect Level Ports 0 - 3 ($0x793)............................................................................... 209
Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) ................................................. 210
Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ...................................... 198
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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Page 19