HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 84

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.2.2.5
5.2.2.5.1
Note:
5.2.2.5.2
5.2.2.6
5.2.2.7
Cortina Systems
SPHY Mode
The SPHY operation mode is selected when bit 21 of the
Global Configuration ($0x700), on page 203
operation for the IXF1104 MAC SPI3 interface.
Data Path
The IXF1104 MAC SPI3 interface has four 8-bit data paths that can support four
independent 8-bit point-to-point connections in SPHY mode (see
MAC port has its own dedicated 8-bit SPI3 data bus, each port has it own status signal
(unlike MPHY). See the For a detailed list of all the signals refer to the SPI3 pin multiplexing
table....
Furthermore since each port has it own dedicated bus the in band port addressing is not
needed. The 8 bit data bus eliminates the need to have separate control signals determine
the number of valid bytes on an EOP.Therefore TSX, RSX, TMOD[1:0] RMOD[1:0] are not
used in SPHY mode.
See
mode signals. Unlike MPHY mode, each port has a dedicated control signal associated with
each of the per-port 8-bit data buses.
page 38
Receive Data Transmission
Packets are transmitted on each port as they become available from the RX FIFO. The
burst length is determined by the setting of per port burst size and the B2B pause settings in
the
inserted, then the entire packet will be burst without any pauses unless the Network
Processor de-asserts RENB. If the B2B_Pause setting calls for the insertion of two pause
cycles on a port, these are inserted after each data burst for that port. The data bursts are
user configurable for each port in the
SPHY Logical Timing
SPI3 interface AC timing for SPHY can be found in
Specifications, on page
associated with SPHY mode. SPHY mode is similar to MPHY mode except the following
signals are not used:
Transmit Timing (SPHY)
Packet transmission starts when TENB and TSOP indicate present data on the bus is the
first word in the packet. All subsequent clocks will contain valid data as long as TENB is
active or until TEOP is asserted. Data transmission can be temporally halted when TENB
goes high then resumed when TENB is low.
®
• TMOD[1:0]
• RMOD[1:0]
• TSX
• RSX
• Address Data appearing on the data bus
IXF1104 4-Port Gigabit Ethernet Media Access Controller
SPI3 Receive Configuration
Table 16, SPI3 MPHY/SPHY Interface, on page 58
provides signal descriptions for all SPI3 signals.
130. Logical timing in the following diagrams illustrates all signals
($0x701). If the B2B pause setting is zero pause cycles
SPI3 Receive Configuration
Table 3, SPI3 Interface Signal Descriptions, on
is set to 1. The SPHY mode is the default
Section 7.2, SPI3 AC Timing
for a complete list of the SPHY
Table 145, SPI3 Transmit and
Figure
($0x701).
16). Since each
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