HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 210

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 151
8.4.11
Note:
Cortina Systems
Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)
Optical Module Register Overview
Table 152
overview of the Optical Module Registers.
All registers in this section are only applicable to ports that are configured in fiber mode.
®
Register Description: This register is used when a change to the operational mode or speed
of the IXF1104 MAC is required. This register ensures that when a change is made that the
internal clocking of the IXF1104 MAC is managed correctly and no unexpected effects of the
operational or speed change are observable on the line interfaces.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
2. Refer to
31:4
Bit
IXF1104 4-Port Gigabit Ethernet Media Access Controller
3
2
1
0
clear; R/W/C = Read/Write, Clear on Write
change the port mode and speed in conjunction with this register.
Name
Reserved
Clock and Interface
Mode Change Enable
Port 3
Clock and Interface
Mode Change Enable
Port 2
Clock and Interface
Mode Change Enable
Port 1
Clock and Interface
Mode Change Enable
Port 0
through
Section 6.1, Change Port Mode Initialization Sequence, on page 124
2
2
2
2
Table 155, I
Reserved
Description
Enables internal clock generator for Port 3 to
sample the
Port_Index + 0x10)
($0x501).
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
Enables internal clock generator for Port 2 to
sample the
Port_Index + 0x10)
($0x501).
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
Enables internal clock generator for Port 1 to
sample the
Port_Index + 0x10)
($0x501).
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
Enables internal clock generator for Port 0 to
sample the
Port_Index + 0x10)
($0x501).
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
2
the
Port_Index + 0x10)
($0x501).
effect.
the
Port_Index + 0x10)
($0x501).
effect.
the
Port_Index + 0x10)
($0x501).
effect.
the
Port_Index + 0x10)
($0x501).
effect.
C Data Ports 0 - 3 ($0x79F), on page 212
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
MAC IF Mode and RGMII Speed ($
and the
and the
and the
and the
and the
and the
and the
and the
Interface Mode
Interface Mode
Interface Mode
Interface Mode
Interface Mode
Interface Mode
Interface Mode
Interface Mode
for the proper sequence to
Type
R/W
R/W
R/W
R/W
RO
provide an
1
0x00000000
0x0000000
Default
0
0
0
0
Page 210