HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 38

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 3
Cortina Systems
SPI3 Interface Signal Descriptions (Sheet 1 of 8)
®
MPHY
TDAT31
TDAT30
TDAT29
TDAT28
TDAT27
TDAT26
TDAT25
TDAT24
TDAT23
TDAT22
TDAT21
TDAT20
TDAT19
TDAT18
TDAT17
TDAT16
TDAT15
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
TDAT9
TDAT8
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TFCLK
TPRTY_0
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Signal Name
SPHY
TDAT7_3
TDAT6_3
TDAT5_3
TDAT4_3
TDAT3_3
TDAT2_3
TDAT1_3
TDAT0_3
TDAT7_2
TDAT6_2
TDAT5_2
TDAT4_2
TDAT3_2
TDAT2_2
TDAT1_2
TDAT0_2
TDAT7_1
TDAT6_1
TDAT5_1
TDAT4_1
TDAT3_1
TDAT2_1
TDAT1_1
TDAT0_1
TDAT7_0
TDAT6_0
TDAT5_0
TDAT4_0
TDAT3_0
TDAT2_0
TDAT1_0
TDAT0_0
TFCLK
TPRTY_0
TPRTY_1
TPRTY_2
TPRTY_3
Designator
Ball
E10
G9
G8
G7
G6
G5
G4
C8
E9
E8
E7
E6
E5
H3
H1
G2
G1
C6
B5
C5
C4
D1
C3
C2
B3
D7
D5
G3
B9
F7
F5
F9
J3
J2
J1
F1
J6
Type
Input
Input
Input
Input
Input
Input
Standard
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Description
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Transmit Clock.
TFCLK is the clock associated with all
transmit signals. Data and control lines are
sampled on the rising edge of TFCLK
(frequency operation range 90 - 133 MHz).
Transmit Parity.
TPRTY indicates odd parity for the TDAT
bus. TPRTY is valid only when a channel
asserts either TENB or TSX. Odd parity is
the default configuration; however, even
parity can be selected (see
Transmit and Global Configuration
($0x700), on page
32-bit Multi-PHY mode: TPRTY_0 is the
parity bit covering all 32 bits.
4 x 8 Single-PHY mode: TPRTY_0:3 bits
correspond to the respective TDAT[3:0]_n
channels.
203).
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
Bits
7:0]
[7:0] for port 0
Table 145, SPI3
Page 38