HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 107

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Figure 24
Note:
5.7.3.3
Cortina Systems
I
Only one optical module I²C access sequence can be run at any given time. If a second
write is carried out to the
before a result is returned for the previous write, the data for the first write is lost. An internal
state machine completes the Optical Module Interface register access for the first write. It
attempts to place the data in the DataRead field and checks to see if the WriteCommand bit
is 00h. If it is not 00h, it discards the data and signals the I²C access state machine to begin
a new cycle using the data from the second write.
I
The following sequence provides an example of writing data to Register Address 0xFF for
Port 3:
All other bits in this register should be set to 0x0.
This data is written into the
interface.
®
2
1. Program the
2. When this register is written and the I
3. The state machines uses the data in the Device ID and Register Address fields to build
4. The I
5. The I
2
C Random Read Transaction
IXF1104 4-Port Gigabit Ethernet Media Access Controller
C Write Operation
a. Enable the I
b. Set the port to be accessed by setting Register bits 17:16 to 0x3.
c. Select a Write access by setting Register bit 15 to 0x0.
d. Set the Device ID Register bits 14:11 to Ah (Atmel compatible).
e. Set the 11-bit register address (Register bits 10:0) to 0FFh.
f.
g. Initiate the I
machine examines the Port Address Select and enables the I
the selected port.
the data frame to be sent to the optical module
the actual data between the IXF1104 MAC and the selected optical module (refer to the
details in
field bits [23:16] of the
I
2
C_Data Line
Enable the I
2
2
C_DATA_WRITE_FSM internal state machine takes over the task of transferring
C_DATA_WRITE_FSM internal state machine uses the data from the Write_Data
(* = DON'T CARE bit for 1k)
Section 5.7.3.4, I²C Protocol Specifics, on page
S
T
A
R
T
I
M
S
B
2
C Control Ports 0 - 3 ($0x79B)
2
ADDRESS
2
2
DEVICE
C transfer by setting Register bit 24 to 0x1.
C block by setting Register bit 25 to 0x1.
C controller by setting Register bit 2 to 0x1.
I
2
DUM M Y WRITE
Table 155 on page 212
C Control Ports 0 - 3 ($0x79B)
I
L
S
B
2
C Control Ports 0 - 3 ($0x79B)
W
W
R
T
E
R
I
/
*
M
S
B
ADDRESS
W ORD
2
C Start bit is at a Logic 1, the I
L
S
B
A
C
K
S
T
A
R
T
with the following information:
and sets the Write_Complete Register bit
M
S
B
ADDRESS
DEVICE
and
in a single cycle via the CPU
L
S
B
I
108).
R
2
E
A
D
C Data Ports 0 - 3 ($0x79F)
A
C
K
2
C_DATA_0:3 output for
DATAn
2
C access state
N
O
C
A
K
O
S
T
P
Page 107