HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 113

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Figure 30
Table 32
5.8.5
5.8.6
Note:
Cortina Systems
Mode 1 Timing
Mode 1 Clock Cycle to Data Bit Relationship
Power-On, Reset, Initialization
The LED interface is disabled at power-on or reset. The system software controller must
enable the LED interface. The internal state machines and output signals are held in reset
until the full IXF1104 4-Port Gigabit Ethernet Media Access Controller device configuration
is completed. This is done by setting the LED_ENABLE bit to a logic 1 (see
Control ($0x509), on page
LED DATA Decodes
The data transmitted on the LED_DATA line is determined by programming the global
operation mode as either fiber or copper.
both fiber and copper MACs.
The data decode of the LED bits is independent of the Physical mode selection.
Table 33
®
LED_CLK Cycle
IXF1104 4-Port Gigabit Ethernet Media Access Controller
LED_LATCH
LED_DATA
LED_CLK
36:38
4:15
2:3
1
LED_DATA# Decodes (Sheet 1 of 2)
LED_DATA#
START BIT
PAD BITS
LED DATA 1-12
PAD BITS
LED_DATA Name
1
2
3
1
2
182). The power-on default for this bit is logic 0.
MAC Port #
3
1
4
0
LED_DATA Description
This bit has no meaning in Mode 1 operation and is shifted out of
the 16-stage shift register chain before the LED_LATCH signal is
asserted.
These bits have no meaning in Mode 1 operation and are shifted
out of the 16-stage shift register chain before the LED_LATCH
signal is asserted.
These bits are the actual data to be transmitted to the 16-stage shift
register chain. The decode for each bit in each mode is defined in
Table 33 on page
The data is INVERTD. Logic 1 (LED ON) = Low.
These bits have no meaning in Mode 1 operation and are latched
into positions 31 and 32 in the shift register chain. These bits are
not considered as valid data and should be ignored. They should
always be a Logic 0 = High.
25
22 23 24 25 26 27 28 29 30
Table 33
Fiber Designation
26
Rx LED—Amber
Rx LED—Green
TX LED—Green
27
113.
shows the data decode of the data for
28
29
30
31
Copper Designation
Activity LED—Green
Link LED—Amber
Link LED—Green
32
33
34
Table 108, LED
35
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