HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 4

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Cortina Systems
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®
Description
First release of this document from Cortina Systems, Inc.
Description
Modified
Table 44, RGMII Power
Added bullet to
single-byte reads and does not guarantee coherency when reading two-byte registers.
Replaced
Modified
Modified
Modified
Modified
Added 552-ball Flip Chip-PBGA (FC-PBGA) and Product Ordering Number information.
Description
Added 552-ball Ceramic Ball Grid Array (CBGA) compliant with RoHS and Product Ordering Number
information.
Added 552-ball Flip Chip-PBGA (FC-PBGA) and Product Ordering Number information.
Modified
Modified
Modified
Modified
Modified
Modified
Modified
uPx_ADD[10:0].
Added paragraphs two and three under
Changed 3.3 V CMOS to 2.5 V CMOS under
Added
Modified
value to V
Modified
max; Changed Min for RFCLK frequency to 90].
Modified
max].
Changed MDC to MDIO Output delay max for t3 for 2.5 MHz from 200 to 300 in
Parameters, on page
Modified
“0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex) from 1 to 0].
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Section 6.2, Disable and Enable Port
Figure 8, Ethernet Frame Format
Table 146, SPI3 Receive Configuration
Table 153, Optical Module Control Ports 0 - 3
Table 154, I
Table 213, I2C Data Ports 0 - 9 ($0x79F)
Table 12, JTAG Interface Signal
Figure 9, PAUSE Frame Format
Figure 11, MPHY Transmit Logical Timing
Figure 12, MPHY Receive Logical Timing
Figure 14, SPHY Transmit Logical Timing
Figure 15, SPHY Receive Logical Timing
Figure 31, Read Timing Diagram - Asynchronous
Table 44, RGMII Power
Table 45, SPI3 Receive Interface Signal Parameters
Table 46, SPI3 Transmit Interface Signal Parameters
Table 88, TX Config Word ($ Port_Index + 0x17)
DD
Figure 57, FC-PBGA Package Diagram (Top and Side View), on page
+ .3].
Section 5.7.3, I²C Module Configuration Interface
2
Revision Date: August 1, 2005 (Sheet 1 of 2)
C Control Ports 0 - 3
140.
[changed V
Revision Date: 28 November 2006
Revision Date: 27-Oct-2005
Revision Number: 10.0
[changed V
Revision Number: 009
Revision Number: 008
CC
to V
Section 5.11, Loopback
Descriptions: changed Standard to 3.3 V LVTTL from 2.5 V CMOS.
[changed Preamble byte count to 7 bytes].
DD in
[changed Preamble byte count to 7 bytes].
($0x79B).
Sequences.
OH
Section 5.12.5, JTAG Clock, on page
, V
I
IH
($0x701).
OL
(changed address from $0x79C to $0x79F).
and I
[updated RDAT[7:0] and RPRTY].
[updated RDAT[31:0]].
[updated TDAT[7:0]].
[updated TDAT[31:0]].
, V
($0x79A): changed default values.
IH
IL
, V
]
[changed default value for the register from
Interface: changed uPx_ADD[12:0] to
IL
minimum conditions to V
[changed RFCLK duty cycle to 45 min and 55
[changed TFCLK duty cycle to 45 min and 55
Modes.
:
The I2C interface only supports random
Table 51, MDIO Timing
216.
122.
DD
and changed V
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IN