HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 3

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Revision History
Cortina Systems
Removed the ordering information from
www.cortina-systems.com.
Updated
(FC-PBGA) package. This chapter includes new package dimensions, part numbers and diagrams.
Removed the marking and ordering information. This information is now available from
Page #
N/A
• Updated
• Updated the Tcdwd and Tcdrh parameter values in
• Updated the Tdatd, Tlath and Tlatl parameter values in
• Replaced the FC-PBGA package drawings in
• Replaced occurences of “2.5V LVTTL” with “2.5V CMOS”.
• Removed caution specifying that “IXF1104 MAC input signals are not 5 V tolerant” in
• Updated signal names shown in
• Updated document with the new corporate logo and template.
• Updated
• Updated
• Updated
• Updated
• Updated the RxRuntErrors counter description. See
• DC coupling is not supported and references were removed.
page 128
LVTTL level tolerant.
Section 9.0, Mechanical Specifications, on page 213
Figure 39, 1000BASE-T Receive Interface Timing, on page
Figure 6, Analog Power Supply Filter Network, on page
Figure 12, MPHY Receive Logical Timing, on page
Table 40, DC Specifications, on page
Figure 39, 1000BASE-T Receive Interface Timing, on page
and added a note stating that “All 3.3V LVTTL input buffers are 5V tolerant, and all 2.5V CMOS input buffers are 3.3V
®
Description
IXF1104 4-Port Gigabit Ethernet Media Access Controller
• Updated the CBGA package side-view drawing
• Added the FCPBGA package side-view drawing
• Updated Electrical specs. on UPX_ADD, UPX_BADD, UPX_DATA, UPX_CS_L, UPX_WR_L, UPX_RD_L,
• Updated the description of the MDIO Soft Reset Register (0x506) to include a definition of a “reset”
View), on page
UPX_RDY_L, UPX_WIDTH, TCLK, SYS_RES_L, and CLK123
and
106, MDIO Soft Reset ($0x506), on page
Table 13 on page
Figure
216).
Table 156, Package Description, on page
31,
Revision Date: 17 September 2008
Revision Date: 14 September 2007
55).
Figure
Revision Date: 01 August 2008
Revision Date: 30 June 2008
Revision Date: 24 April 2007
Revision Date: 12 May 2008
Revision Date: 20 July 2007
Section 9.3.2, Plastic Ball Grid Array Package Diagram, on page
128.
Revision Number: 11.0
32,
Table 53, CPU Interface AC Signal Parameters, on page
page
Revision 13.2
Revision 13.1
Revision 13.0
Revision 12.2
Revision 12.1
Revision 12.0
Figure
Table 57, LED Interface AC Timing Parameters, on page
to reflect the change to the Flip Chip-Plastic Ball Grid Array
169.
82.
182).
47and
63.
(Figure 55, CBGA Package Side View
Figure 48
(Figure 57, FC-PBGA Package Diagram (Top and Side
137.
137.
213. This information is now available from
to match the signal tables.
www.cortina-systems.com.
(Table 7 on page
Section 7.1, DC Specifications, on
51,
Table 12 on page
Diagram).
143.
216.
147.
(Table
Page 3
55,