UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 52

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

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50
Data memory
space
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
Program RAM area
Program
memory
space
RAM spcae in
which instruction
can be fetched
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security
Common
area
Bank
area
When boot swap is used:
Settings).
F E F F H
F E E 0 H
F E D F H
F A F F H
F F F F H
F B 0 0 H
F F 0 0 H
F 7 F F H
F 8 0 0 H
B F F F H
7 F F F H
E 7 F F H
C 0 0 0 H
8 0 0 0 H
E 8 0 0 H
0 0 0 0 H
Special function registers
Internal high-speed RAM
Internal expansion RAM
General-purpose
(memory bank 0)
32 x 8 bits
Flash memory
Figure 3-6. Memory Map ( PD78F0376D, 78F0386D)
registers
Flash memory
1024 x 8 bits
4096 x 8 bits
16384 x 8 bits
32768 x 8 bits
256 x 8 bits
Reserved
Reserved
(SFR)
CHAPTER 3 CPU ARCHITECTURE
IDs to 0085H to 008EH.
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
User’s Manual U17504EJ2V0UD
(Memory bank 2)
(Memory bank 1)
(Memory bank 3)
0 F F F H
0 0 8 E H
7 F F F H
1 0 8 E H
0 0 8 F H
1 0 8 F H
1 0 0 0 H
0 7 F F H
0 0 8 5 H
0 0 8 4 H
0 0 7 F H
0 0 3 F H
0 0 0 0 H
1 0 7 F H
0 8 0 0 H
0 0 8 0 H
0 0 4 0 H
1 0 8 5 H
1 0 8 4 H
1 0 8 0 H
Option byte area
On-chip debug security
On-chip debug security
Option byte area
CALLT table area
Vector table area
CALLF entry area
ID setting area
ID setting area
Program area
Program area
1905 x 8 bits
Program area
2048 x 8 bits
64 x 8 bits
64 x 8 bits
5 x 8 bits
10 x 8 bits
5 x 8 bits
10 x 8 bits
Note1
Note1
Note1
Note1
1 F F F H
Boot cluster 0
Boot cluster 1
Note2