UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 382

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

16.5.14 Communication reservation
380
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition
is automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected
by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IIC0 before the
stop condition is detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0
(IICS0)) after STT0 is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 16-6.
Figure 16-20 shows the communication reservation timing.
released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1).
CLX0
0
0
0
0
0
0
0
0
1
1
1
SMC0
0
0
0
0
1
1
1
1
1
1
1
CHAPTER 16 SERIAL INTERFACE IIC0
CL01
0
0
1
1
0
0
1
1
0
0
1
Table 16-6. Wait Periods
User’s Manual U17504EJ2V0UD
CL00
0
1
0
1
0
1
0
1
0
1
0
46 clocks
86 clocks
172 clocks
34 clocks
30 clocks
60 clocks
12 clocks
18 clocks
36 clocks
Wait Period