UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 145

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(3) CPU operating with subsystem clock (D) after reset release (A)
(A)
Status Transition
(A)
10 MHz)
(A)
f
(A)
20 MHz)
(A)
f
Status Transition
(A)
(A)
XH
XH
Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers.
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
10 MHz)
20 MHz)
(B)
(B)
(B)
(B)
(B)
(B)
(B)
CHAPTER 29 ELECTRICAL SPECIFICATIONS).
(C) (X1 clock: 1 MHz
(C) (external main clock: 1 MHz
(C) (X1 clock: 10 MHz < f
(C) (external main clock: 10 MHz <
(D) (XT1 clock)
(D) (external subsystem clock)
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
:
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
f
XH
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
XH
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17504EJ2V0UD
SFR registers do not have to be set (default status after reset release).
AMPH
XTSTART
0
0
1
1
0
1
0
EXCLK
0
1
0
1
EXCLKS
1
0
OSCSEL
1
1
1
1
SFR Register Setting
OSCSELS
MSTOP
0
0
0
0
1
1
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
1
1
CSS
MCM0
1
1
1
1
1
1
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