UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 467

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0374, 78F0375, 78F0376, 78F0376D, 78F0384, 78F0385, 78F0386, AND 78F0386D ONLY)
Address: FF62H, FF63H, FF64H, FF65H
Symbol
MDA0H
Symbol
MDA0L
(1) Remainder data register 0 (SDR0)
Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of
(2) Multiplication/division data register A0 (MDA0H, MDA0L)
Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when
Address: FF60H, FF61H
Symbol
SDR0
SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the
remainder of an operation result in the division mode.
SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation sets SDR0 to 0000H.
MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the
division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L).
MDA
MDA
031
015
2. SDR0 is reset when the operation is started (when DMUE is set to 1).
2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of
3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed.
Figure 18-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L)
SDR
015
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
multiplier/divider control register 0 (DMUC0) is set to 81H).
multiplier/divider control register 0 (DMUC0) is 1).
executed, but the result is undefined.
MDA
MDA
030
014
SDR
014
MDA
MDA
029
013
Figure 18-2. Format of Remainder Data Register 0 (SDR0)
SDR
FF65H (MDA0HH)
FF63H (MDA0LH)
013
After reset: 0000H
MDA
MDA
028
012
FF61H (SDR0H)
SDR
012
MDA
MDA
027
011
SDR
011
After reset: 0000H, 0000H
MDA
MDA
026
010
User’s Manual U17504EJ2V0UD
SDR
010
R
MDA
MDA
025
009
SDR
009
MDA
MDA
024
008
SDR
008
MDA
MDA
023
007
SDR
007
R/W
MDA
MDA
022
006
SDR
006
MDA
MDA
021
005
Even in this case, the operation is
SDR
FF64H (MDA0HL)
FF62H (MDA0LL)
005
MDA
MDA
020
004
FF60H (SDR0L)
SDR
004
MDA
MDA
019
003
SDR
003
MDA
MDA
018
002
SDR
002
MDA
MDA
017
001
SDR
001
MDA
MDA
016
000
SDR
000
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