UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 260

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(2) 10-bit A/D conversion result register (ADCR)
258
Symbol
Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT.
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0000H.
Sampling
INTAD
ADCS
timing
Address: FF08H, FF09H
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
ADCS
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may
become undefined.
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
Figure 12-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Figure 12-5. A/D Converter Sampling and A/D Conversion Timing
period
1 or ADS rewrite
Wait
Note
CHAPTER 12 A/D CONVERTER ( PD78F037x ONLY)
FF09H
clear
SAR
After reset: 0000H
Read the conversion result following conversion completion before
Sampling time
User’s Manual U17504EJ2V0UD
Conversion time
R
conversion time
Successive
generation
to ADCR,
Transfer
INTAD
0
clear
SAR
0
FF08H
Conversion time
0
Sampling time
0
0
0