UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 313

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UPD78F0386GK-8EU-A

Manufacturer Part Number
UPD78F0386GK-8EU-A
Description
MCU 96KB FLASH 5KB RAM
Manufacturer
Renesas Electronics America
Series
78K0/Lx2r
Datasheet

Specifications of UPD78F0386GK-8EU-A

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
14.4 Operation of Serial Interface UART6
14.4.1 Operation stop mode
addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and
5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
(1) Register used
Address: FF50H After reset: 01H R/W
Serial interface UART6 has the following two modes.
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
Notes 1.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation.
Remark To use the R
Symbol
ASIM6
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Operation stop mode
Asynchronous serial interface (UART) mode
2.
To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1.
FUNCTIONS.
POWER6
The output of the T
POWER6 = 0 during transmission.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
POWER6
RXE6
TXE6
0
<7>
Note 1
0
0
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Disables transmission operation (synchronously resets the transmission circuit).
Disables reception (synchronously resets the reception circuit).
X
D6/P14 and T
TXE6
<6>
X
D6 pin goes high and the input from the R
CHAPTER 14 SERIAL INTERFACE UART6
RXE6
<5>
X
D6/P13 pins as general-purpose port pins, see CHAPTER 4
User’s Manual U17504EJ2V0UD
Enables/disables operation of internal operation clock
Note 2
.
PS61
4
Enables/disables transmission
Enables/disables reception
PS60
3
X
CL6
D6 pin is fixed to high level when
2
SL6
1
ISRM6
0
PORT
311

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