UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 425

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

IIC bus
Master
Slave
IIC shift
register 0
IIC shift
register
SDA0
LSDA
SCL0
LSCL
(3) Operation
SDA
SCL
Start condition
Start condition
The operation flow when transmitting write data twice is shown below.
Steps <1> to <11> correspond to <1> to <11> in Figure 16-31.
<1> The start condition is transmitted.
<2> The slave ID is transmitted (from the 1st to 7th clocks).
<3> R/W information (0) is transmitted (at the 8th clock).
<4> An acknowledge signal is received (at the rising edge of the 9th clock).
<5> The write start address is transmitted (from the 1st to 8th clocks following <4>).
<6> An acknowledge signal is received (at the rising edge of the 9th clock).
<7> Write data is transmitted (first time) (from the 1st to 8th clocks following <6>).
<8> An acknowledge signal is received (at the rising edge of the 9th clock).
<9> Write data is transmitted (second time) (from the 1st to 8th clocks following <8>).
<10> An acknowledge signal is received (at the rising edge of the 9th clock).
<11> The stop condition is transmitted.
Figures 16-32 shows the timing chart of the write operation.
xxH
(The address is automatically incremented by 1.)
xxH
Write to IIC shift register 0
Setup
xxH
ID6
ID6
1
1
1
xxH
xxH
Figure 16-32. Timing Chart of Write Operation
W
8
R
8
8
CHAPTER 16 SERIAL INTERFACE IIC0
ACK
ACK
xxH
9
9
9
xxH
Write to IIC shift register 0
User’s Manual U17504EJ2V0UD
Setup
xxH
0
1
0
1
1
xxH
xxH
A0
A0
8
8
8
ACK
ACK
xxH
9
9
9
xxH
Write to IIC shift register 0
Setup
xxH
WD7
WD7
1
1
1
xxH
xxH
WD0
WD0
8
8
8
xxH
ACK
ACK
9
9
9
xxH
xxH
Stop condition
Stop condition
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