UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 475

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Maskable
Interrupt
Notes 1.
Type
2.
3.
4.
Priority
Default
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 24 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
10
11
12
13
14
15
16
17
18
19
20
21
PD78F037x only.
0
1
2
3
4
5
6
7
8
9
Note 1
INTTMH1
INTTMH0
INTTM50
INTTM000
INTTM010
INTTM51
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTSRE6
INTSR6
INTST6
INTCSI10/
INTST0
INTAD
INTSR0
INTWTI
INTKR
INTWT
Name
Note 4
Low-voltage detection
Pin input edge detection
UART6 reception error generation
End of UART6 reception
End of UART6 transmission
End of CSI10 communication/end of UART0
transmission
Match between TMH1 and CMP01
(when compare register is specified)
Match between TMH0 and CMP00
(when compare register is specified)
Match between TM50 and CR50
(when compare register is specified)
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
End of A/D conversion
End of UART0 reception or reception error
generation
Watch timer reference time interval signal
Match between TM51 and CR51
(when compare register is specified)
Key interrupt detection
Watch timer overflow
Table 19-1. Interrupt Source List (1/2)
CHAPTER 19 INTERRUPT FUNCTIONS
Interrupt Source
User’s Manual U17504EJ2V0UD
Trigger
Note 3
Internal
External
Internal
External
Internal
External
Internal/
Address
000AH
000CH
000EH
001AH
001CH
001EH
002AH
002CH
002EH
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
0026H
0028H
Vector
Table
Configuration
Type
Basic
(C)
(A)
(B)
(A)
(A)
Note 2
473