UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 229

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UPD78F0386GK-8EU-A

Manufacturer Part Number
UPD78F0386GK-8EU-A
Description
MCU 96KB FLASH 5KB RAM
Manufacturer
Renesas Electronics America
Series
78K0/Lx2r
Datasheet

Specifications of UPD78F0386GK-8EU-A

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LCD, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
(TOLEV1 = 0)
<1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
<5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn
<6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output default.
Count clock
counter Hn
8-bit timer
INTTMH1
CMP01
CMP11
TMHE1
TOH1
clock to count up. At this time, the TOHn output remains default.
to the count clock.
counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
output level is inverted. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
Remark n = 0, 1
00H 01H 02H
<1>
(e) Operation by changing CMP1n (CMP1n = 02H
02H
Figure 8-12. Operation Timing in PWM Output Mode (4/4)
80H
<2>
CHAPTER 8 8-BIT TIMERS H0 AND H1
A5H 00H 01H 02H 03H
02H (03H)
<3>
User’s Manual U17504EJ2V0UD
<2>’
<4>
A5H
03H
A5H 00H 01H 02H 03H
03H, CMP0n = A5H)
<5>
A5H 00H
<6>
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