UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 157

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.
Falling edge
Rising edge
No capture operation
Falling edge
Rising edge
Both rising and falling edges
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or
TI010 pin valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2).
CR000 Capture Trigger
CR000 Capture Trigger
2. ES001, ES000:
ES101, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
2. If CR000 is cleared to 0000H in the free-running mode and in the clear mode using the valid
3. When P01 is used as the valid edge input of the TI010 pin, it cannot be used as the timer
4. When CR000 is used as a capture register, read data is undefined if the register read time
5. Do not rewrite CR000 during TM00 operation.
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
of TM00 and CR000.
edge of the TI000 pin, an interrupt request (INTTM000) is generated when the value of CR000
changes from 0000H to 0001H following TM00 overflow (FFFFH). In addition, INTTM000 is
generated after a match between TM00 and CR000, after detecting the valid edge of the
TI010 pin, and the timer is cleared by a one-shot trigger.
output (TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge
input of the TI010 pin.
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U17504EJ2V0UD
TI000 Pin Valid Edge
TI010 Pin Valid Edge
ES001
ES101
0
0
1
0
0
1
ES000
ES100
1
0
1
0
1
1
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