UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 140

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

138
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock
<1>
<2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register)
<3> Selecting the CPU clock division ratio (PCC register)
The internal high-speed oscillation clock can be stopped in the following two ways.
(a) To execute a STOP instruction
Executing the STOP instruction to set the STOP mode
Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
<1> Setting of peripheral hardware
<2> Setting the X1 clock oscillation stabilization time after standby release
<3> Executing the STOP instruction
Set the main system clock and peripheral hardware clock using XSEL and MCM0.
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
Restarting oscillation of the internal high-speed oscillation clock
(See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation
clock).
Oscillating the high-speed system clock
(This setting is required when using the high-speed system clock as the peripheral hardware clock.
See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high-
XSEL
CSS
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 21 STANDBY FUNCTION).
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
0
0
1
0
speed system clock is already operating.
MCM0
PCC2
0
1
0
0
0
0
0
1
Other than above
Internal high-speed oscillation clock
(f
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
RH
PCC1
)
CHAPTER 5 CLOCK GENERATOR
0
0
1
1
0
Main System Clock (f
User’s Manual U17504EJ2V0UD
PCC0
0
1
0
1
0
Note
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
XP
)
/2 (default)
/2
/2
/2
2
3
4
CPU Clock (f
Internal high-speed oscillation clock
(f
High-speed system clock (f
RH
Peripheral Hardware Clock (f
)
Note
CPU
) Selection
XH
)
PRS
)