UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 299

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event
capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting R
Reception interrupt
Reception processing is as follows.
Figure 14-3 shows the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
The input source of the reception port input (R
Edge detection
<1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception
<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
<3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter
<4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
Capture timer
(INTSR6)
mode.
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is
output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF
reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored.
00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field
(see 6.4.3 Pulse width measurement operation (timer 00 only)). Detection of errors OVE6, PE6, and
FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift
register and RXB6 is not performed. The shift register holds the reset value FFH.
then re-set baud rate generator control register 6 (BRGC6).
reception of the checksum field and to set the SBF reception mode again.
LIN Bus
(INTP0)
(input)
R
X
D6
Disable
signal frame
<1>
Wakeup
Enable
CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-2. LIN Reception Operation
Disable
SBF reception
break field
User’s Manual U17504EJ2V0UD
13-bit
Sync
<2>
X
D6) can be input to the external interrupt (INTP0) and 16-bit
<3>
Sync field
reception
SF
Enable
<4>
reception
Identifier
field
ID
Data field
reception
X
D6 and INTP0/TI000 externally.
Data
Data field Checksum
reception
Data
reception
field
Data
<5>
297