UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 148

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(10) HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
146
(B)
(C)
(D)
Status Transition
(D)
10 MHz)
(D)
f
(D)
20 MHz)
(D)
f
(B)
(C)
XH
XH
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
10 MHz
20 MHz)
HALT mode (F) set while CPU is operating with high-speed system clock (C)
HALT mode (G) set while CPU is operating with subsystem clock (D)
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(E)
already been set.
(F)
(G)
(H)
(C) (X1 clock: 1 MHz
(C) (external main clock: 1 MHz
(C) (X1 clock: 10 MHz < f
(C) (external main clock: 10 MHz <
(I)
(Setting sequence of SFR registers)
CHAPTER 29 ELECTRICAL SPECIFICATIONS).
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
Setting Flag of SFR Register
Status Transition
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
f
XH
(Setting sequence)
XH
AMPH
Unnecessary if these registers
CHAPTER 5 CLOCK GENERATOR
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
0
0
1
1
User’s Manual U17504EJ2V0UD
Note
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
are already set
EXCLK
0
1
0
1
OSCSEL
1
1
1
1
with the high-speed
MSTOP
Unnecessary if the
CPU is operating
system clock
0
0
0
0
Setting
Must not be
Must not be
Setting
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Executing STOP instruction
XSEL
Unnecessary if this register
1
1
1
1
Note
is already set
MCM0
1
1
1
1
CSS
0
0
0
0