UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 247

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
Remarks 1. f
5. The watchdog timer does not stop during self-programming of the flash memory and
WDCS2
depending on the set value of bit 0 (LSROSC) of the option byte.
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
EEPROM
overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
2. ( ): f
2. The watchdog timer does not stop during self-programming of the flash memory and
RL
is prohibited.
EEPROM emulation. During processing, the interrupt acknowledge time is delayed.
Set the overflow time and window size taking this delay into consideration.
TM
: Internal low-speed oscillation clock frequency
Table 10-3. Setting of Overflow Time of Watchdog Timer
WDCS1
emulation. During processing, the interrupt acknowledge time is delayed. Set the
RL
0
0
1
1
0
0
1
1
= 264 kHz (MAX.)
Watchdog timer operation stops.
Oscillator Can Be Stopped by Software)
CHAPTER 10 WATCHDOG TIMER
WDCS0
LSROSC = 0 (Internal Low-Speed
0
1
0
1
0
1
0
1
User’s Manual U17504EJ2V0UD
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)
245