UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 945

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Memory
bank
switching
function
(products
whose flash
memory is
at least
96 KB only)
Port
function
Function
BANK: Memory
bank select
register
Memory bank
P02/SO11,
P04/SCK11
P10/SCK10/TxD0,
P12/SO10
P13/TxD6
Port 2
P31/INTP2/
OCD1A
Port 4
P60, P61
P62
Port 7
Details of
Function
Be sure to change the value of the BANK register in the common area (0000H to
7FFFH).
If the value of the BANK register is changed in the bank area (8000H to BFFFH), an
inadvertent program loop occurs in the CPU. Therefore, never change the value of
the BANK register in the bank area.
Instructions cannot be fetched between different memory banks.
Branching and accessing cannot be directly executed between different memory
banks. Execute branching or accessing between different memory banks via the
common area.
Allocate interrupt servicing in the common area.
An instruction that extends from 7FFFH to 8000H can only be executed in memory
bank 0.
To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation
mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the
default status (00H).
To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial
operation mode register 10 (CSIM10) and serial clock selection register 10
(CSIC10) to the default status (00H)
To use P13/TxD6 as general-purpose port, clear bit 0 (TXDLV6) of synchronous
serial interface control register 6 (ASICL6) to 0 (normal output of TxD6).
Make the AV
digital port.
For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to “1”, and
bits 6 and 7 of P2 to “0”.
In the product with an on-chip debug function (
sure to pull the P31/INTP2/OCD1A pin down before a reset release, to prevent
malfunction.
Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug
function (
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.183).
For the 38-pin products of 78K0/KC2, be sure to set bits 0 and 1 of PM4 and P4 to
“0”.
A through current flows through P60 and P61 if an intermediate potential is input to
these pins, because the input buffer is also turned on when P60 and P61 are in
output mode. Consequently, do not input an intermediate potential when P60 and
P61 are in output mode.
A through current flows through P62 if an intermediate potential is input to this pin,
because the input buffer is also turned on when P62 is in output mode.
Consequently, do not input an intermediate potential when P62 is in output mode.
For the 38-pin products of 78K0/KC2, be sure to set bits 2 and 3 of PM7 and P7 to
“0”.
μ
PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is
REF
pin the same potential as the V
Cautions
μ
DD
PD78F05xxD and 78F05xxDA), be
pin when port 2 is used as a
APPENDIX D LIST OF CAUTIONS
p. 150
p. 151
p. 151
p. 151
p. 151
p. 164
p. 175
p. 175
p. 181
p. 182
p. 183
p. 183
p. 187
p. 190
p. 191
p. 195
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