UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 492

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(1) Transmit buffer register 1n (SOTB1n)
(2) Serial I/O shift register 1n (SIO1n)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SI11/P03
SCK11/P04
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial
operation mode register 1n (CSIM1n) is 1.
The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to
the serial output pin (SO1n).
SOTB1n can be written or read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication).
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0.
During reception, the data is read from the serial input pin (SI1n) to SIO1n.
Reset signal generation clears this register to 00H.
Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication).
Remark n = 0:
SSI11
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a low
2. In the slave mode, reception is started when data is read from SIO11 with a low level input to the
f
f
f
f
f
f
PRS
PRS
PRS
PRS
PRS
PRS
f
PRS
level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2)
Communication operation.
SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication operation.
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/2
/2
/2
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2
3
4
5
6
7
Transmit data
controller
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
PM04
Serial I/O shift
register 11 (SIO11)
Figure 16-2. Block Diagram of Serial Interface CSI11
8
Output latch
Internal bus
(P04)
Output latch
Transmit buffer
register 11 (SOTB11)
Clock start/stop controller &
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
clock phase controller
Transmit controller
8
selector
Output
output
SO11
Output latch
(P02)
INTCSI11
PM02
SSI11
SO11/P02
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