UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 416

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(2) 10-bit A/D conversion result register (ADCR)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Note For details of wait period, see CHAPTER 36 CAUTIONS FOR WAIT.
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
Symbol
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register. The higher 8 bits of the
conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
ADCR
Sampling
INTAD
ADCS
timing
Address: FF08H, FF09H
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
peripheral hardware clock (f
ADCS
Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
period
1 or ADS rewrite
Wait
Note
FF09H
clear
SAR
After reset: 0000H
Sampling
PRS
) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT.
Conversion time
R
Successive conversion
generation
to ADCR,
Transfer
INTAD
0
CHAPTER 13 A/D CONVERTER
clear
SAR
0
FF08H
Conversion time
0
Sampling
0
0
0
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