UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 701

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(2) Low-voltage detection level selection register (LVIS)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FFBFH
Symbol
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
The generation of a reset signal other than an LVI reset clears this register to 00H.
LVIS
Cautions 3. When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI detection
Notes 1. The value of LVIS is not reset but retained as is, upon a reset by LVI. It is cleared to 00H upon
Cautions 1. Be sure to clear bits 4 to 7 to “0”.
7
0
LVIS3
Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
2. Do not set V
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
After reset: 00H
4. With the conventional-specification products (
other resets.
2. Do not change the value of LVIS during LVI operation.
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
4. With the conventional-specification products (
voltage, an INTLVI signal is generated and LVIIF becomes 1.
reset has been generated, do not write values to LVIS and LVIM when LVION = 1.
voltage (V
reset has been generated, do not write values to LVIS and LVIM when LVION = 1.
6
0
LVIS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LVI10
Note 1
EXLVI
to V
5
0
LVIS1
R/W
= 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LVI15
for (A2) grade products.
4
0
LVIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LVIS3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LVI0
LVI1
LVI2
LVI3
LVI4
LVI5
LVI6
LVI7
LVI8
LVI9
LVI10
LVI11
LVI12
LVI13
LVI14
LVI15
3
(4.24 V ±0.1 V)
(4.09 V ±0.1 V)
(3.93 V ±0.1 V)
(3.78 V ±0.1 V)
(3.62 V ±0.1 V)
(3.47 V ±0.1 V)
(3.32 V ±0.1 V)
(3.16 V ±0.1 V)
(3.01 V ±0.1 V)
(2.85 V ±0.1 V)
(2.70 V ±0.1 V)
(2.55 V ±0.1 V)
(2.39 V ±0.1 V)
(2.24 V ±0.1 V)
(2.08 V ±0.1 V)
(1.93 V ±0.1 V)
CHAPTER 25 LOW-VOLTAGE DETECTOR
LVIS2
2
μ
μ
Detection level
PD78F05xx and 78F05xxD), after an LVI
PD78F05xx and 78F05xxD), after an LVI
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
LVIS1
1
LVIS0
0
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