UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 421

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
13.4 A/D Converter Operations
13.4.1 Basic operations of A/D converter
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator.
<2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to
<3> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
<4> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<5> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
<6> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<7> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<8> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
<9> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
<10> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
<11> Comparison is continued in this way up to bit 0 of SAR.
<12> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<13> Repeat steps <6> to <12>, until ADCS is cleared to 0.
Caution Make sure the period of <1> to <5> is 1
Remark Two types of A/D conversion result registers are available.
input mode by using port mode register 2 (PM2).
(<6> to <12> are operations performed by hardware.)
sampled voltage is held until the A/D conversion operation has ended.
AV
voltage comparator. If the analog input is greater than (1/2) AV
analog input is smaller than (1/2) AV
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <5>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
from <4>.
REF
• ADCR (16 bits): Store 10-bit A/D conversion value
• ADCRH (8 bits): Store 8-bit A/D conversion value
by the tap selector.
REF
REF
REF
μ
s or longer, and start <5>. To change a channel of A/D conversion, start
, the MSB is reset to 0.
μ
s or more.
REF
, the MSB of SAR remains set to 1. If the
CHAPTER 13 A/D CONVERTER
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