UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 560

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Caution When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0)
Remark
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it
• Cannot be set to 1 at the same time as start condition trigger (STT0).
• SPT0 bit can be set to 1 only when in master mode.
• When WTIM0 has been cleared to 0, if SPT0 bit is set to 1 during the wait period that follows output of eight clocks, note that
• Setting SPT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1
during the wait period following the output of eight clocks, and SPT0 bit should be set to 1 during the wait period that follows
the output of the ninth clock.
SPT0
0
1
of the IICC0 register is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is
cleared (reception status) and the SDA0 line is set to high impedance. Release the wait performed
while the TRC bit is 1 (transmission status) by writing to the IIC shift register.
Bit 0 (SPT0) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been
notified of final reception.
during the wait period that follows output of the ninth clock.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4)
Stop condition trigger
CHAPTER 18 SERIAL INTERFACE IIC0
Condition for setting (SPT0 = 1)
• Set by instruction
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