UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 516

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1. Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O
Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed.
2. Do not start communication with the external clock from the SCKA0 pin when the internal high-speed
Address: FF90H
Symbol
CSIMA0
Figure 17-2. Format of Serial Operation Mode Specification Register 0 (CSIMA0)
2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above are
3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the
shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset.
oscillation clock and high-speed system clock are stopped while the CPU operates with the
subsystem clock, or when in the STOP mode.
asynchronously initialized.
registers.
value of the buffer RAM will be retained.
MASTER0
CSIAE0
CSIAE0
RXEA0
TXEA0
ATM0
ATE0
DIR0
< >
0
1
0
1
0
1
0
1
0
1
0
1
0
1
After reset: 00H
CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and
asynchronously resets the internal circuit
CSIA0 operation enabled
1-byte communication mode
Automatic communication mode
Single transfer mode (stops at the address specified by the ADTP0 register)
Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer)
Slave mode (synchronous with SCKA0 input clock)
Master mode (synchronous with internal clock)
Transmit operation disabled (SOA0: Low level)
Receive operation disabled
Receive operation enabled
MSB
LSB
Transmit operation enabled
ATE0
Control of automatic communication operation enable/disable
ATM0
Automatic communication mode specification
R/W
Control of transmit operation enable/disable
Control of receive operation enable/disable
Control of CSIA0 operation enable/disable
CSIA0 master/slave mode specification
To set CSIAE0 = 1 again, be sure to re-set the initialized
MASTER0 TXEA0
First bit specification
< >
CHAPTER 17 SERIAL INTERFACE CSIA0
Note 1
RXEA0
.
< >
Note 2
DIR0
0
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