DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 687

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 18.3 Registers/Parameters and Target Modes
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
18.7.1
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a power-on reset.
(1)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Register/Parameter
Programming/
erasing interface
registers
Programming/
erasing interface
parameters
RAM emulation
Bit
Bit Name
Initial Value
R/W
Flash Code Control/Status Register (FCCS)
2. The setting may be required according to the combination of initiation mode and read
Programming/Erasing Interface Registers
target memory MAT.

R
7
1
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
DPFR
FPFR
FPEFEQ 
FMPAR
FMPDR
FEBS
RAMER

R
6
0
Down-
load
O
O
O
O

O
O






R
5
0
Initiali-
zation







O
O




FLER
R
4
0
Section 18 Flash Memory (0.18-µm F-ZTAT Version)
Program-
ming



O
O*


O

O
O


1

R
3
0
Rev. 2.00 Jun. 28, 2007 Page 661 of 864
Erasure



O
O*


O



O

1

R
2
0
Read




O*









2
R
1
0
REJ09B0341-0200
RAM
Emulation












O
(R)/W
SCO
0
0